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ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E
Data Sheet December 16, 2008 FN6824.0
QUAD, 16.5kV ESD Protected, 3.0V to 5.5V, Low Power, RS-422 Transmitters
The Intersil ISL32x7xE are 16.5kV IEC61000-4-2 ESD Protected, 3.0V to 5.5V powered, QUAD transmitters for balanced communication using the RS-422 standard. These drivers have very low output leakage currents (10A), so they present a low load to the RS-422 bus. Driver (Tx) outputs are tri-statable, and incorporate a hot plug feature to keep them disabled during power-up and down. Versions are available with a common EN/EN (`172 pinout), a two channel EN12/EN34 (`174 pinout), or a versatile combination of individual and group channel enables (see Table 1). The ISL32372E, ISL32374E utilize slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or from unterminated stubs in multidrop and multipoint applications. Drivers on the other versions are not limited, so they can achieve the 10Mbps or 32Mbps data rates. All versions are offered in Industrial and Extended Industrial (-40C to +125C) temperature ranges. A 50% smaller footprint (compared to the TSSOP) is available with the ISL32179E's QFN package. This device also features a logic supply pin (VL), that sets the switching points of the enable and DI inputs to be compatible with a lower supply voltage in mixed voltage systems. Two speed select pins allow the ISL32179E user to select from three slew rate options for 460kbps, 10Mbps, or 32Mbps data rates. Individual channel and group enable pins increase the ISL32179E's flexibility.
Features
* IEC61000 ESD Protection on RS-422 Outputs . . 16.5kV - Class 3 ESD Level on all Other Pins . . . . . . 12kV HBM - High Machine Model ESD Level on all Pins . . . . . 700V * Wide Supply Range . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V * Specified for +125C Operation * Available in Industry Standard Pinouts (`172/'174) or in a Space Saving QFN (ISL32179E) with Added Features * Logic Supply Pin (VL) Eases Operation in Mixed Supply Systems (ISL32179E Only) * User Selectable Data Rate (ISL32179E Only) * Hot Plug - Tx Outputs Remain Three-state During Power-up and Power-Down * Low Tx Leakage Allows > 256 Devices on the Bus * High Data Rates . . . . . . . . . . . . . . . . . . . . . up to 32Mbps * Low Quiescent Supply Current . . . . . . . . . . 0.8mA (Max) - Low Shutdown Supply Current . . . . . . . . . . . . . . . 60A * Current Limiting and Thermal Shutdown for Driver Overload Protection * Tri-statable Tx Outputs * 5V Tolerant Logic Inputs When VCC 5V * Pb-free (RoHS compliant)
Applications
* Telecom Equipment * Motor Controllers / Encoders * Programmable Logic controllers * Industrial/Process Control Networks
TABLE 1. SUMMARY OF FEATURES PART NUMBER ISL32172E ISL32272E ISL32372E ISL32174E ISL32274E ISL32374E ISL32179E DATA RATE (Mbps) 32 10 0.46 32 10 0.46 32, 10, 0.46 SLEW-RATE LIMITED? NO NO YES NO NO YES SELECTABLE HOT PLUG? YES YES YES YES YES YES YES TX ENABLE TYPE EN, EN EN, EN EN, EN EN12, EN34 EN12, EN34 EN12, EN34 INDIV. AND GROUP ENABLES QUIESCENT ICC (mA) <1 <1 <1 <1 <1 <1 <1 LOW POWER SHUTDOWN? NO NO NO NO NO NO YES PIN COUNT 16 16 16 16 16 16 24
FUNCTION 4 Tx 4 Tx 4 Tx 4 Tx 4 Tx 4 Tx 4 Tx
VL PIN? NO NO NO NO NO NO YES
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Pinouts
ISL32172E, ISL32272E, ISL32372E (16 LD N-SOIC, TSSOP) TOP VIEWS
DI1 1 Y1 2 Z1 3 EN 4 Z2 5 Y2 6 DI2 7 GND 8 D D D D 16 VCC 15 DI4 14 Y4 13 Z4 12 EN 11 Z3 10 Y3 9 DI3
ISL32174E, ISL32274E, ISL32374E (16 LD N-SOIC, TSSOP) TOP VIEWS
DI1 1 Y1 2 Z1 3 EN12 4 Z2 5 Y2 6 DI2 7 GND 8 D D D D 16 VCC 15 DI4 14 Y4 13 Z4 12 EN34 11 Z3 10 Y3 9 DI3
ISL32179E (24 LD QFN) TOP VIEW
SHDNEN
VCC
DI1
24 Z1 EN1 EN2 EN Z2 Y2 1 2 3 4 5 6 7 DI2
23
22
21
20
19 18 Y4 17 Z4 16 EN4 15 EN3 14 EN 13 Z3
8 SPA
9 GND
10 SPB
11 DI3
12 Y3
Ordering Information
PART NUMBER (Notes 1, 2) ISL32172EFBZ ISL32172EFVZ ISL32172EIBZ ISL32172EIVZ ISL32174EFBZ ISL32174EFVZ ISL32174EIBZ ISL32174EIVZ ISL32179EFRZ ISL32179EIRZ ISL32272EFBZ ISL32272EFVZ ISL32272EIBZ ISL32272EIVZ PART MARKING ISL32172 EFBZ 32172 EFVZ ISL32172 EIBZ 32172 EIVZ ISL32174 EFBZ 32174 EFVZ ISL32174 EIBZ 32174 EIVZ 321 79EFRZ 321 79EIRZ ISL32272 EFBZ 32272 EFVZ ISL32272 EIBZ 32272 EIVZ TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +85 -40 to +85 -40 to +125 -40 to +125 -40 to +85 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +125 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP 24 Ld QFN 24 Ld QFN 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP PKG. DWG. # M16.15 MDP0044 M16.15 MDP0044 M16.15 MDP0044 M16.15 MDP0044 L24.4x4C L24.4x4C M16.15 MDP0044 M16.15 MDP0044
2
DI4
Y1
VL
FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Ordering Information (Continued)
PART NUMBER (Notes 1, 2) ISL32274EFBZ ISL32274EFVZ ISL32274EIBZ ISL32274EIVZ ISL32372EFBZ ISL32372EFVZ ISL32372EIBZ ISL32372EIVZ ISL32374EFBZ ISL32374EFVZ ISL32374EIBZ ISL32374EIVZ NOTES: 1. Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020 PART MARKING ISL32274 EFBZ 32274 EFVZ ISL32274 EIBZ 32274 EIVZ ISL32372 EFBZ 32372 EFVZ ISL32372 EIBZ 32372 EIVZ ISL32374 EFBZ 32374 EFVZ ISL32374 EIBZ 32374 EIVZ TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +85 -40 to +85 -40 to +125 -40 to +125 -40 to +85 -40 to +85 -40 to +125 -40 to +125 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP PKG. DWG. # M16.15 MDP0044 M16.15 MDP0044 M16.15 MDP0044 M16.15 MDP0044 M16.15 MDP0044 M16.15 MDP0044
Truth Tables
ISL32172E, ISL32272E, ISL32372E INPUTS EN X 1 0 EN 0 X 1 DIX 1/0 0/1 X ZX 0/1 1/0 Z OUTPUTS YX 1/0 0/1 Z INPUTS
ISL32179E OUTPUTS COMMENTS
ENX EN EN DIX SPA SPB ZX YX 0 X 1 1 1 1 X 0 X 1 X 1 X 1 X 1 0 X 0 X 0 X X X 1/0 0/1 1/0 0/1 1/0 0/1 X X 1 1 0 0 X* X* X X 1 1 1 1 0 0 Z Z
Z Chan X outputs disabled Z All outputs disabled
0/1 1/0 Individual ENX controls chan X (32Mbps) 1/0 0/1 0/1 1/0 Individual ENX controls chan X (10Mbps) 1/0 0/1 0/1 1/0 Individual ENX controls chan X (460kbps) 1/0 0/1
NOTE: Z = Tri-state
ISL32174E, ISL32274E, ISL32374E INPUTS EN12 EN34 DIX 0 0 1 1 0 1 0 1 X 1/0 1/0 1/0 Z1 Z Z 0/1 0/1 Y1 Z Z 1/0 1/0 Z2 Z Z 0/1 0/1 OUTPUTS Y2 Z Z 1/0 1/0 Z3 Z 0/1 Z 0/1 Y3 Z 1/0 Z 1/0 Z4 Z 0/1 Z 0/1 Y4 Z 1/0 Z 1/0
1 1
NOTE: *Keep SPA = 1 for lowest current in SHDN. If using individual channel enables, and the SHDN mode, connect EN and EN to VCC for the lowest SHDN current. ISL32179E enters SHDN when SHDNEN = 1 and all channels are disabled. Z = Tri-state.
NOTE: Z = Tri-state
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Pin Descriptions
PIN EN, EN FUNCTION Group driver output enables, that are internally pulled high to VCC. All ISL32x72E driver outputs, Y and Z, are enabled by driving EN high OR EN low, and the outputs are high impedance when EN is low AND EN is high (i.e., if using only the active high EN, connect EN directly to VCC or VL; if using only the active low EN, connect EN directly to GND). On the ISL32179E accomplish group enable by connecting all the ENX pins to VCC or VL, and then use the EN or EN pin as previously described. If the group driver enable function isn't required (see Note), connect EN to VCC, or connect EN to GND. (ISL32x72E and ISL32179E only) Paired driver output enables, that are internally pulled high to VCC. Driving EN12 (EN34) high enables Channel 1 and 2 (3 and 4) outputs (Y and Z). Driving EN12 (EN34) low disables Channel 1 and 2 (3 and 4) outputs. If the driver enable function isn't required (see Note), connect EN12 and EN34 to VCC. (ISL32x74E only) Individual driver output enables that are internally pulled high to VCC. Forcing ENx high (along with EN high OR EN low) enables the channel X outputs (Y and Z). Driving ENX low disables the Channel X outputs, regardless of the states of EN and EN. Connect both EN and EN to VCC for the lowest SHDN current if utilizing SHDN mode (see SHDNEN below). If the individual driver enable function isn't required (see Note), connect ENX to VCC. (ISL32179E only) Low power SHDN mode enable. A high level allows the ISL32179E to enter a low power mode when all channels are disabled. A low level prevents the device from entering the low power mode. (ISL32179E only) Driver input. A low on DI forces the corresponding channel's output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. Speed select inputs that are internally pulled-high. See ISL32179E Truth Table on page 3. (ISL32179E only) Ground connection. This is also the potential of the QFN thermal pad. 16.5kV IEC61000-4-2 ESD Protected RS-422 level, noninverting transmitter output. 16.5kV IEC61000-4-2 ESD Protected RS-422 level, inverting transmitter output. System power supply input (3.0V to 5.5V). On devices with a VL pin, power-up VCC first. Logic power supply input. Connecting the VL pin to the lower voltage power supply of a logic device (e.g., UART or controller) interfacing with the ISL32179E tailors its logic pin (DI, EN (all varieties), SHDNEN, and SP) VIL/VIH levels to values compatible with the lower supply voltage. Power-up this supply after VCC, and keep VL VCC. (ISL32179E only)
EN12, EN34
ENx
SHDNEN
DIx
SPA, SPB GND Yx Zx VCC VL
NOTE: Unused EN pins of any type should not be left floating, even though they have internal pull-ups.
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Typical Operating Circuits (1 of 4 Channels Shown)
NETWORK USING GROUP ENABLES
+3.3V TO 5V + 16 VCC ISL32x73E 3 RO 12 EN A R B 2 1 RT 2 3 Y Z D DI 1 EN 4 EN 12 GND 8 EN 4 GND 8 0.1F 0.1F + 16 VCC ISL32x72E +3.3V TO 5V
NETWORK USING PAIRED ENABLES
+3.3V TO 5V + 16 VCC ISL32x75E 3 RO1 4 EN12 A1 2 R B1 1 RT 2 3 0.1F 0.1F + 16 VCC ISL32x74E Y1 Z1 D DI1 1 +3.3V TO 5V
EN12 4
GND 8
GND 8
NETWORK WITH VL PIN FOR INTERFACING TO LOWER VOLTAGE LOGIC DEVICES
1.8V 21 VCC +3.3V TO 5V + 22 VCC VL 9 SHDNEN 15 EN 4 EN 1 RO1 2 EN1 GND 10 ISL32x77E A1 24 R B1 23 RT 24 1 0.1F 0.1F + 20 VL SHDNEN 22 ISL32179E EN 14 EN1-EN4 2,3,15,16 Y DI 23 Z D EN 4 VCC GND 9 21 VCC +3.3V TO 5V 2.5V
LOGIC DEVICE (P, ASIC, UART)
LOGIC DEVICE P, ASIC, UART)
USING INDIVIDUAL CHANNEL ENABLES AND CONFIGURED FOR LOWEST SHDN SUPPLY CURRENT NOTE: POWER-UP VCC BEFORE VL
USING ACTIVE HIGH GROUP ENABLE AND CONFIGURED FOR LOWEST SHDN SUPPLY CURRENT NOTE: POWER-UP VCC BEFORE VL
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E
Absolute Maximum Ratings
VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V VL to GND (ISL32179E Only) . . . . . . . . . . . . . -0.3V to (VCC +0.3V) Input Voltages DI, EN (all varieties) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Output Voltages Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Output Current Y, Z (Per Output, Continuous, TJ 125C) . . . . . . . . . . . . 100mA ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 16 Ld SOIC Package (Note 3) . . . . . . . 80 N/A 16 Ld TSSOP Package (Note 3) . . . . . 105 N/A 24 Ld QFN Package (Notes 4, 5). . . . . 42 5 Maximum Junction Temperature (Plastic Package) . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range ISL32x7xEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C ISL32x7xEI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 for details. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Test Conditions: VCC = 3.0V to 3.6V and 4.5V to 5.5V; VL = VCC (ISL32179E only); Typicals are at VCC = 3.3V or VCC = 5V, TA = +25C; Unless Otherwise Specified.(Notes 6, 10) SYMBOL TEST CONDITIONS TEMP (C) MIN (Note 9) TYP MAX (Note 9) UNITS
PARAMETER DC CHARACTERISTICS Differential VOUT
VOD
No Load RL = 100 (RS-422) (see Figure 1) VCC 3V VCC 4.5V
Full Full Full Full Full Full
2.5 2 3 2.4 -
2.6 4 2.7 0.2 0.01
VCC 0.4 0.2 V V V V V
Single-Ended VOUT (Y or Z) Change in Magnitude of Driver Differential VOUT for Complementary Output States Driver Common-Mode VOUT Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States Input High Voltage (Logic Pins, Note 14)
VO VOD
IO = -20mA, VOH IO = 20mA, VOL RL = 100 (see Figure 1)
VOC VOC
RL = 100 (see Figure 1) RL = 100 (see Figure 1)
Full Full
-
2.6 0.01
3 0.2
V V
VIH1 VIH2 VIH2E VIH3 VIH4 VIH5 VIH6
VL = VCC if ISL32179E
VCC 3.6V VCC 5.5V, DI VCC 5.5V, ENs
Full Full Full Full Full Full 25 Full Full Full Full 25
2.2 2.7 2.4 2 1.6 0.72*VL -
0.45*VL 0.25*VL
0.8 0.6 0.6 0.22*VL -
V V V V V V V V V V V V
2.7V VL < 3.0V (ISL32179E Only) 2.3V VL < 2.7V (ISL32179E Only) 1.6V VL < 2.3V (ISL32179E Only) 1.5V VL < 1.6V (ISL32179E Only) VL = VCC if ISL32179E VL 2.7V (ISL32179E Only) 2.3V VL < 2.7V (ISL32179E Only) 1.6V VL < 2.3V (ISL32179E Only) 1.5V VL < 1.6V (ISL32179E Only)
Input Low Voltage (Logic Pins, Note 14)
VIL1 VIL2 VIL3 VIL4 VIL5
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E
Electrical Specifications
Test Conditions: VCC = 3.0V to 3.6V and 4.5V to 5.5V; VL = VCC (ISL32179E only); Typicals are at VCC = 3.3V or VCC = 5V, TA = +25C; Unless Otherwise Specified.(Notes 6, 10) (Continued) SYMBOL IIN1 IIN2 IIN3 Output Leakage Current (Y, Z) IOZ TEST CONDITIONS DIX = 0V or VCC SP, EN, EN, ENX, SHDNEN = 0V or VCC EN12, EN34 = 0V or VCC EN = 0, VCC = 0V to 5.5V, -0.25 VO 6V EN = 0, VCC = 3V to 5.5V, VO = 0V to VCC Driver Short-Circuit Current, VO = High or Low Thermal Shutdown Threshold SUPPLY CURRENT No-Load Supply Current Shutdown Supply Current ESD PERFORMANCE RS-422 Pins (Y, Z) IEC61000-4-2, From Bus Pins to GND Air Gap Contact 25 25 25 25 25 16.5 9 15 12 700 kV kV kV kV V ICC ISHDN DI = 0V or VCC, EN = 1 DI = 0V or VCC, All outputs disabled (Note 15), SHDNEN = 1 (ISL32179E only) Full Full 0.6 60 0.8 90 mA A IOSD1 TSD EN = 1, VY or VZ = 0V (Note 7) EN = 1, VY or VZ = VCC (Note 7) TEMP (C) Full Full Full Full 25 (Note 16) Full Full Full MIN (Note 9) -1 -15 -30 -10 -8 -30 TYP 9 18 160 MAX (Note 9) UNITS 1 15 30 10 8 30 150 200 A A A A nA nA mA mA C
PARAMETER Logic Input Current
Human Body Model, From Bus Pins to GND All Pins HBM, per MIL-STD-883 Method 3015 Machine Model DRIVER SWITCHING CHARACTERISTICS (ISL32372E, ISL32374E, ISL32179E, 460kbps) Maximum Data Rate Driver Single-Ended Output Delay Driver Single-Ended Output Skew Ch-to-Ch Output Delay Skew Part-to-Part Output Delay Skew Driver Differential Output Skew Driver Differential Rise or Fall Time Driver Enable to Output High Driver Enable to Output Low Driver Disable from Output High Driver Disable from Output Low Driver Enable from SHDN to High Driver Enable from SHDN to Low fMAX tSSK tSKCC tSKPP tDSK tR, tF tZH tZL tHZ tLZ tSDH tSDL VOD = 1.5V, CD = 820pF (see Figure 4) RDIFF = 100, CD = 50pF (see Figure 2) (Figure 2, Note 11) (Figure 2, Note 8) RDIFF = 100, CD = 50pF (see Figure 2) RDIFF = 100, CD = 50pF (see Figure 2) SW = GND (see Figure 3, Note 12) SW = VCC (see Figure 3, Note 12) SW = GND (see Figure 3) SW = VCC (see Figure 3) ISL32179E Only, SW = GND (see Figure 3, Note 13) ISL32179E Only, SW = VCC (see Figure 3, Note 13)
Full Full Full Full Full Full Full Full Full Full Full Full Full
460 60 -
4000 90 55 60 2 100 -
300 150 200 300 60 220 200 200 100 100 750 750
kbps ns ns ns ns ns ns ns ns ns ns ns ns
tPLH, tPHL RDIFF = 100, CD = 50pF (see Figure 2)
DRIVER SWITCHING CHARACTERISTICS (ISL32272E, ISL32274E, ISL32179E, 10Mbps) Maximum Data Rate Driver Single-Ended Output Delay Driver Single-Ended Output Skew Ch-to-Ch Output Delay Skew Part-to-Part Output Delay Skew Driver Differential Output Skew Driver Differential Rise or Fall Time Driver Enable to Output High Driver Enable to Output Low fMAX tSSK tSKCC tSKPP tDSK tR, tF tZH tZL VOD = 1.5V, CD = 400pF (see Figure 4) RDIFF = 100, CD = 50pF (see Figure 2) (Figure 2, Note 11) (Figure 2, Note 8) RDIFF = 100, CD = 50pF (see Figure 2) RDIFF = 100, CD = 50pF (see Figure 2) SW = GND (see Figure 3, Note 12) SW = VCC (see Figure 3, Note 12) Full Full Full Full Full Full Full Full Full 10 7 20 13 2 6 2 11 25 9 12 20 6 20 20 20 Mbps ns ns ns ns ns ns ns ns
tPLH, tPHL RDIFF = 100, CD = 50pF (see Figure 2)
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E
Electrical Specifications
Test Conditions: VCC = 3.0V to 3.6V and 4.5V to 5.5V; VL = VCC (ISL32179E only); Typicals are at VCC = 3.3V or VCC = 5V, TA = +25C; Unless Otherwise Specified.(Notes 6, 10) (Continued) SYMBOL tHZ tLZ tSDH tSDL TEST CONDITIONS SW = GND (see Figure 3) SW = VCC (see Figure 3) ISL32179E Only, SW = GND (see Figure 3, Note 13) ISL32179E Only, SW = VCC (see Figure 3, Note 13) TEMP (C) Full Full Full Full MIN (Note 9) TYP MAX (Note 9) UNITS 20 20 750 750 ns ns ns ns
PARAMETER Driver Disable from Output High Driver Disable from Output Low Driver Enable from SHDN to High Driver Enable from SHDN to Low
DRIVER SWITCHING CHARACTERISTICS (ISL32172E, ISL32174E, ISL32179E, 32Mbps) Maximum Data Rate Driver Single-Ended Output Delay Driver Single-Ended Output Skew Ch-to-Ch Output Delay Skew Part-to-Part Output Delay Skew Driver Differential Output Skew Driver Differential Rise or Fall Time Driver Enable to Output High Driver Enable to Output Low Driver Disable from Output High Driver Disable from Output Low Driver Enable from SHDN to High Driver Enable from SHDN to Low NOTES: 6. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 7. Applies to peak current. See "Typical Performance Curves" beginning on page 12 for more information. 8. tSKPP is the magnitude of the difference in propagation delays of the specified terminals of two units tested with identical test conditions (VCC, temperature, etc.). 9. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. EN = 0 indicates that the output(s) under test are disabled via the appropriate logic pin settings. EN = 1 indicates that the logic pins are set to enable the output(s) under test. 11. Channel-to-channel skew is the magnitude of the worst case delta between any two propagation delays of any two outputs on the same IC, at the same test conditions. 12. For ISL32179E, keep SHDNEN low to avoid entering SHDN. 13. Keep SHDNEN high to enter SHDN when all transmitters are disabled (ISL32179E only). 14. Logic Pins are the DIs, the enable variants, and SHDNEN. 15. Only one of the SPX pins low, plus EN1-EN4 low with EN and EN high, or EN low and EN high with EN1-EN4 high. 16. Temperature range is -20C to +40C. fMAX tSSK tSKCC tSKPP tDSK tR, tF tZH tZL tHZ tLZ tSDH tSDL VOD = 1.5V, CD = 100pF (see Figure 4) RDIFF = 100, CD = 50pF (see Figure 2) (Figure 2, Note 11) (Figure 2, Note 8) RDIFF = 100, CD = 50pF (see Figure 2) RDIFF = 100, CD = 50pF (see Figure 2) SW = GND (see Figure 3, Note 12) SW = VCC (see Figure 3, Note 12) SW = GND (see Figure 3) SW = VCC (see Figure 3) ISL32179E Only, SW = GND (see Figure 3, Note 13) ISL32179E Only, SW = VCC (see Figure 3, Note 13) Full Full Full Full Full Full Full Full Full Full Full Full Full 32 3 50 8 1 3 0.5 7 15 3.5 5.5 8 2 12 20 20 20 20 750 750 Mbps ns ns ns ns ns ns ns ns ns ns ns ns
tPLH, tPHL RDIFF = 100, CD = 50pF (see Figure 2)
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Test Circuits and Waveforms
VCC OR VL
EN DI D Y Z VOD
RL/2
RL/2
VOC
FIGURE 1. DC DRIVER TEST CIRCUITS
LOWER OF VCC OR VL 1.5V 0V tPHL VOH 50% tSSK DI D Y SIGNAL GENERATOR Z RDIFF CD OUT (Z) tDDLH DIFF OUT (Y - Z) 90% 0V 10% tR tSSK = |tPLH(Y OR Z) - tPHL(Z OR Y)| 50% 50% VOL tDDHL 90% 0V 10% tF tDSK = |tDDLH - tDDHL| +VOD -VOD tPHL tSSK tPLH 50% VOL VOH
DI tPLH OUT (Y) VCC OR VL EN
1.5V
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
EN DI D SIGNAL GENERATOR Y 50pF SW Z 110 VCC GND tZH tHZ OUTPUT HIGH VOH - 0.5V 50% 0V tZL tSDL OUT (Y, Z) 50% OUTPUT LOW VOL + 0.5V V OL tLZ VCC VOH 3V OR VL EN 1.5V 1.5V 0V tSDH OUT (Y, Z)
PARAMETER tHZ tLZ tZH (Note 12) tZL (Note 12) tSDH (Note 13) tSDL (Note 13)
OUTPUT Y/Z Y/Z Y/Z Y/Z Y/Z Y/Z
DI 1/0 0/1 1/0 0/1 1/0 0/1
SW GND VCC GND VCC GND VCC
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES
9
FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Test Circuits and Waveforms (Continued)
VCC OR VL EN
+
LOWER OF VCC OR VL DI 0V
DI D
Z 100 Y CD VOD
-
SIGNAL GENERATOR
DIFF OUT (Y - Z) -VOD
+VOD
0V
FIGURE 4A. TEST CIRCUIT FIGURE 4. DRIVER DATA RATE
FIGURE 4B. MEASUREMENT POINTS
Application Information
RS-422 is a differential (balanced) data transmission standard for use in long haul or noisy environments. RS-422 is a point-to-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus.
Driver Features
These RS-422 drivers are differential output devices that deliver at least 2V across a 100 load. The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI. The 460kbps driver outputs are slew rate limited to minimize EMI, and to reduce reflections in unterminated or improperly terminated networks. Outputs of the 10Mbps and 32Mbps drivers are not limited, so faster output transition times allow the higher data rates.
EN3 and EN4 together. For individual channel enables, again connect EN and EN high, and drive the appropriate ENX (active high) for the particular channel. All of the enable pins incorporate pull-up resistors to VCC, but unused enable pins of any type should be externally connected high, rather than being left floating. Connecting to VCC is the best choice, but VL may be utilized as long as SHDN power isn't a primary concern (for each VL connected input, ICC increases by ((VCC - VL)/600k). If VCC or VL transients might exceed 7V, then inserting a series resistor between the input(s) and the supply limits the current that will flow if the input's ESD protection starts conducting.
1 OF 4 CHANNELS ENX EN EN VCC VCC VCC
CHX EN
Driver Enable Functions
All product types include functionality to allow disabling of the Tx outputs. The ISL32x72E types feature group (all four Tx) enable functions that are active high (EN) or active low (EN). Drivers enable when EN = 1, or when EN = 0, and they disable only when EN = 0 and EN = 1. ISL32x74E versions use active high paired enable functions (EN12 and EN34) that enable (when high) or disable (when low) the corresponding pairs of Tx. All four of these enable pins have internal pull-up resistors to VCC, but unused enable pins that need to be high (e.g., EN when using the EN input for enable control, or EN12 and EN34 when using always enabled drivers) should always be connected externally to VCC. If VCC transients might exceed 7V, then inserting a series resistor between the input(s) and VCC limits the current that will flow if the input's ESD protection starts conducting. The ISL32179E has the most flexible enable scheme. Its six enable pins allow for group, paired, or individual channel enable control. Figure 5 details the ISL32179E's internal enable logic. To utilize a group enable function, connect all the ENx pins high, and handle the EN and EN pins as described in the previous paragraph. For paired enables, connect EN and EN high (for the lowest current in SHDN mode, if SHDN is used) and tie EN1 and EN2 together, and
FIGURE 5. ISL32179E ENABLE LOGIC
Wide Supply Range
These ICs are designed to operate with a wide range of supply voltages from 3.0V to 5.5V, and they meet the RS-422 specifications for that full supply voltage range. 5.5V TOLERANT LOGIC PINS Logic input pins (driver inputs, enables, SHDNEN) contain no ESD nor parasitic diodes to VCC (nor to VL), so they withstand input voltages exceeding 5.5V regardless of the VCC and VL voltages. Input voltages up to 7V are easily tolerated.
Logic Supply (VL Pin, ISL32179E Only)
Note: Power-up VCC before powering up the VL supply. If unused enable pins are connected to VL rather than to VCC, then a small ICC ((VCC - VL)/600k) will flow due to the internal pull-up resistor connecting to VCC. The ISL32179E includes a VL pin that powers the logic inputs (driver inputs, enables, SHDNEN). These pins interface with "logic" devices such as UARTs, ASICs, and
FN6824.0 December 16, 2008
10
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E
controllers, and today most of these devices use power supplies significantly lower than 3.3V. Thus, the logic device's low VOH might not exceed the VIH of a 3.3V or 5V powered DI or enable input. Connecting the VL pin to the power supply of the logic device (as shown in Figure 6) reduces the DI and enable input switching points to values compatible with the logic device's output levels. Tailoring the logic pin input switching points to the supply voltage of the UART, ASIC, or controller eliminates the need for a level shifter/translator between the two ICs.
VCC = +3.3V VCC = +2V
Hot Plug Function
When a piece of equipment powers up, there is a period of time where the processor or ASIC driving the RS-422 control lines (EN, EN, ENx) is unable to ensure that the RS-422 Tx outputs remain disabled. If the equipment is connected to the bus, a driver activating prematurely during power-up may drive invalid data on the bus. To avoid this scenario, this family incorporates a "Hot Plug" function. During power-up, circuitry monitoring VCC ensures that the Tx outputs remain disabled for a period of time, regardless of the state of the enable pins. This gives the processor/ASIC a chance to stabilize and drive the RS-422 control lines to the proper states.
ESD Protection
VIH 2 DI VOH 2 VIH 2 VOH 2 TXD
EN GND
DEN GND
ISL32172E VCC = +3.3V
UART/PROCESSOR VCC = +2V
VL DI VIH = 0.85V VOH 2 VIH = 0.85V VOH 2 TXD
All pins on these devices include class 3 (>12kV) Human Body Model (HBM) ESD protection structures, but the RS-422 pins (driver outputs) incorporate advanced structures allowing them to survive ESD events in excess of 15kV HBM, and 16.5kV to IEC61000-4-2. The RS-422 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, and without degrading the RS-422 common mode range of -0.3V to +6V. This built-in ESD protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present.
EN GND
DEN GND
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-422 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The IEC61000 standard's lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device's RS-422 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-422 port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The RS-422 pins withstand 16.5kV air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap
ISL32179E
UART/PROCESSOR
FIGURE 6. USING VL PIN TO ADJUST LOGIC LEVELS
VL can be anywhere from VCC down to 1.5V, and Table 2 indicates typical VIH and VIL values for various VL settings so the user can ascertain whether or not a particular VL voltage meets his needs.
TABLE 2. VIH AND VIL vs VL FOR VCC = 3.3V OR 5V VL (V) 1.6 2 2.3 2.7 2.7 3.3 VIH (V) 0.7 0.85 1.1 1.4 (DI), 1.1 (ENs) 2 2.2 VIL (V) 0.45 0.6 0.75 0.85 0.8 0.8
11
FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E
discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than 9kV. Devices in this family survive 9kV contact discharges on the RS-422 pins. exceeds the RS-422 specification. A novel design sets the short circuit current limit depending on the VCC value, so unlike some competing devices, the VCC = 5V short circuit current is only slightly higher than the corresponding VCC = 3.3V level (see Figure 12). In the event of a major short circuit condition, devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically re-enable after the die temperature drops about 20. If the fault persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared.
Data Rate, Cables, and Terminations
RS-422 is intended for network lengths up to 4000', but the maximum system data rate decreases as the transmission length increases. Devices operating at 32Mbps handle lengths up to 328' (100m) in 5V systems, and lengths up to 200' (62m) in 3.3V systems (see Figures 31 and 32). The 460kbps versions can operate at full data rates with lengths of thousands of feet. Note that system jitter requirements may limit a network to shorter distances. Twisted pair is the cable of choice for RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in RS-422 ICs. Proper termination is imperative, when using the 10Mbps or 32Mbps devices, to minimize reflections. Short networks using the 460kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (multiple receivers on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible.
High Temperature Operation
With TA = +125C and VCC = 5.5V, four 100 differentially terminated drivers in the TSSOP package put the IC at the edge of its maximum allowed junction temperature. Using larger termination resistors, a lower maximum supply voltage, or one of the packages with a lower thermal resistance (JA) provides more safety margin. When designing for +125C operation, be sure to measure the application's switching current, and include this in the thermal calculations.
Low Power Shutdown Mode (ISL32179E Only)
These BiCMOS transmitters all use a fraction of the power required by their bipolar counterparts, but the QFN version includes a shutdown feature that reduces the already low quiescent ICC by 90%. The ISL32179E enters shutdown (SHDN) whenever the SHDNEN pin is high and all four drivers are disabled (see "Pin Descriptions" on page 4). Note that the enable times from SHDN are longer than the enable times when the IC isn't in SHDN.
Built-In Driver Overload Protection
The driver output stages incorporate short circuit current limiting circuitry which ensures that the output current never
Typical Performance Curves
110 DRIVER OUTPUT CURRENT (mA) 100 90 80 70 60 50 40 30 20 10 0 0 0.5 VCC = 3.3V +125C +125C +85C +25C +85C
VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only.
4.3 DIFFERENTIAL OUTPUT VOLTAGE (V) RDIFF = 100 4.1 3.9 3.7 3.5 3.3 3.1 2.9 2.7 2.5 -40 -25 -10 5 VCC = 3.3V VCC = 5V
+25C
VCC = 5V 4.5 5.0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 DIFFERENTIAL OUTPUT VOLTAGE (V)
20 35 50 65 TEMPERATURE (C)
80
95
110 125
FIGURE 7. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT VOLTAGE
FIGURE 8. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Typical Performance Curves
120 DRIVER OUTPUT CURRENT (mA) 100 +25C 80 +85C +125C 60 40 20 VOL 0 0 0.5 1.0 1.5 2.0 2.5 Y OR Z OUTPUT VOLTAGE (V) VOH 3.0 3.3 0 0 +125C VCC = 3.3V RDIFF = +25C +85C
VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued)
140 +85C DRIVER OUTPUT CURRENT (mA) 120 100 80 60 40 20 VOL 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Y OR Z OUTPUT VOLTAGE (V) 4.0 VOH 4.5 5.0 +85C +25C +125C VCC = 5V RDIFF = +25C +125C
FIGURE 9. DRIVER SINGLE-ENDED (Y OR Z) OUTPUT CURRENT vs OUTPUT VOLTAGE
FIGURE 10. DRIVER SINGLE-ENDED (Y OR Z) OUTPUT CURRENT vs OUTPUT VOLTAGE
500 VCC = 5V 450 OUTPUT CURRENT (mA) EN = VCC
150
VCC = 5V VCC = 3.3V Y OR Z = LOW
100
400 ICC (A)
50
350
0
300
-50 VCC = 3.3V
250 VCC = 3.3V 200 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125
-100 VCC = 5V -150 -0.5 0 Y OR Z = HIGH
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT VOLTAGE (V)
FIGURE 11. SUPPLY CURRENT vs TEMPERATURE
FIGURE 12. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT VOLTAGE
94 VL = 1.6V TO VCC 92 PROPAGATION DELAY (ns) 90 SKEW (ns) 88 86 84 tDDHL 82 80 -40
60 tSSK 50 VCC = 5V
40 tSSK 30 VL = 1.6V TO VCC 20 VCC = 3.3V
tDDLH
10 tDSK VCC = 3.3V OR 5V 80 95 110 125
-25
-10
5
20 35 50 65 TEMPERATURE (C)
80
95
110
125
0 -40
-25
-10
5
20 35 50 65 TEMPERATURE (C)
FIGURE 13. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL32372E, ISL32374E, ISL32179E, 460kbps OPTION)
FIGURE 14. DRIVER SKEW vs TEMPERATURE (ISL32372E, ISL32374E, ISL32179E, 460kbps OPTION)
13
FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Typical Performance Curves
20 19 PROPAGATION DELAY (ns) 18 17 16 15 14 13 12 11 10 -40 -25 tDDLH tDDHL -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 0.5 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 1.0 VL = VCC = 3.3V OR 5V tDSK tDDHL tDDLH SKEW (ns) VL = 1.6V, VCC = 3.3V OR 5V 2.0 2.5 tSSK
VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued)
3.0 VL = 1.6V to VCC
1.5
FIGURE 15. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL32272E, ISL32274E, ISL32179E, 10Mbps OPTION)
16 15 PROPAGATION DELAY (ns) 14 13 tDDLH 12 11 10 9 8 7 6 -40 tDDHL -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 tDDLH VL 3V, VCC = 3.3V OR 5V tDDHL VL = 1.6V, VCC = 3.3V OR 5V
FIGURE 16. DRIVER SKEW vs TEMPERATURE (ISL32272E, ISL32274E, ISL32179E, 10Mbps OPTION)
1.2
1.0 tDSK VL = 1.6V, VCC = 3.3V OR 5V
0.8 SKEW (ns)
0.6
VL = 1.6V to VCC, VCC = 3.3V OR 5V tSSK
0.4 tDSK 0.2 VL 3V, VCC = 3.3V OR 5V
0 -40
-25
-10
5
20 35 50 65 TEMPERATURE (C)
80
95
110 125
FIGURE 17. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL32172E, ISL32174E, ISL32179E, 32Mbps OPTION)
VCC = 3.3V, VL = 1.6V TO VCC DRIVER OUTPUT (V) DI 0 3.0 1.5 Y 0 VH = VCC OR VL DRIVER OUTPUT (V) 3 2 1 0 -1 -2 -3 TIME (40ns/DIV) Y-Z Z RDIFF = 100, CD = 50pF VH DRIVER INPUT (V)
FIGURE 18. DRIVER SKEW vs TEMPERATURE (ISL32172E, ISL32174E, ISL32179E, 32Mbps OPTION)
VCC = 3.3V, VL = 1.6V TO VCC DRIVER OUTPUT (V) DI
RDIFF = 100, CD = 50pF VH 0 DRIVER INPUT (V)
3.0 1.5
Y Z
0 VH = VCC OR VL 3 2 1 0 -1 -2 -3 Y-Z
DRIVER OUTPUT (V)
TIME (40ns/DIV)
FIGURE 19. DRIVER WAVEFORMS, LOW TO HIGH (ISL32372E, ISL32374E, ISL32179E)
FIGURE 20. DRIVER WAVEFORMS, HIGH TO LOW (ISL32372E, ISL32374E, ISL32179E)
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Typical Performance Curves
VCC = 5V, VL = 1.6V TO VCC DRIVER OUTPUT (V) DI 0 5.0 Z 2.5 Y 0 5 4 2 0 -2 -4 -5 TIME (40ns/DIV) Y-Z VH = VCC OR VL DRIVER OUTPUT (V)
VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued)
VCC = 5V, VL = 1.6V TO VCC DRIVER OUTPUT (V) VH DRIVER INPUT (V) DI 0 5.0 Y 2.5 Z 0 VH = VCC OR VL 5 4 2 0 -2 -4 -5 TIME (40ns/DIV) Y-Z RDIFF = 100, CD = 50pF VH DRIVER INPUT (V) DRIVER INPUT (V) DRIVER INPUT (V)
RDIFF = 100, CD = 50pF
DRIVER OUTPUT (V)
FIGURE 21. DRIVER WAVEFORMS, LOW TO HIGH (ISL32372E, ISL32374E, ISL32179E)
VCC = 3.3V, VL = 1.6V TO VCC DRIVER OUTPUT (V) DI 0 3.0 1.5 Y 0 3 2 1 0 -1 -2 -3 TIME (10ns/DIV) Y-Z VH = VCC OR VL Z RDIFF = 100, CD = 50pF VH DRIVER INPUT (V)
FIGURE 22. DRIVER WAVEFORMS, HIGH TO LOW (ISL32372E, ISL32374E, ISL32179E)
VCC = 3.3V, VL = 1.6V TO VCC DRIVER OUTPUT (V) DI 0 3.0 1.5 Z 0 VH = VCC OR VL DRIVER OUTPUT (V) 3 2 1 0 -1 -2 -3 Y-Z Y RDIFF = 100, CD = 50pF VH
DRIVER OUTPUT (V)
TIME (10ns/DIV)
FIGURE 23. DRIVER WAVEFORMS, LOW TO HIGH (ISL32272E, ISL32274E, ISL32179E)
VCC = 5V, VL = 1.6V TO VCC DRIVER OUTPUT (V) DI 0 5.0 Z 2.5 Y 0 VH = VCC OR VL DRIVER OUTPUT (V) 5 4 2 0 -2 -4 -5 TIME (10ns/DIV) Y-Z RDIFF = 100, CD = 50pF VH DRIVER INPUT (V)
FIGURE 24. DRIVER WAVEFORMS, HIGH TO LOW (ISL32272E, ISL32274E, ISL32179E)
VCC = 5V, VL = 1.6V TO VCC DRIVER OUTPUT (V) DI 0 5.0 Y 2.5 Z 0 VH = VCC OR VL DRIVER OUTPUT (V) 5 4 2 0 -2 -4 -5 TIME (10ns/DIV) Y-Z RDIFF = 100, CD = 50pF VH
FIGURE 25. DRIVER WAVEFORMS, LOW TO HIGH (ISL32272E, ISL32274E, ISL32179E)
FIGURE 26. DRIVER WAVEFORMS, HIGH TO LOW (ISL32272E, ISL32274E, ISL32179E)
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Typical Performance Curves
VCC = 3.3V, VL = 1.6V TO VCC DRIVER OUTPUT (V) DI 0 3.0 1.5 Y 0 VH = VCC OR VL DRIVER OUTPUT (V) DRIVER OUTPUT (V) 3 2 1 0 -1 -2 -3 TIME (10ns/DIV) Y-Z
VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued)
VCC = 3.3V, VL = 1.6V TO VCC DI RDIFF = 100, CD = 50pF VH 0 3.0 1.5 Z 0 VH = VCC OR VL 3 2 1 0 -1 -2 -3 Y-Z Y DRIVER INPUT (V) DRIVER INPUT (V)
VH DRIVER INPUT (V)
Z
DRIVER OUTPUT (V)
RDIFF = 100, CD = 50pF
TIME (10ns/DIV)
FIGURE 27. DRIVER WAVEFORMS, LOW TO HIGH (ISL32172E, ISL32174E, ISL32179E)
FIGURE 28. DRIVER WAVEFORMS, HIGH TO LOW (ISL32172E, ISL32174E, ISL32179E)
DRIVER OUTPUT (V)
VCC = 5V, VL = 1.6V TO VCC DI
RDIFF = 100, CD = 50pF VH 0 DRIVER INPUT (V) DRIVER OUTPUT (V)
VCC = 5V, VL = 1.6V TO VCC DI
RDIFF = 100, CD = 50pF VH 0
5.0 Z 2.5 Y 0 5 4 2 0 -2 -4 -5 TIME (10ns/DIV) Y-Z VH = VCC OR VL
5.0 Y 2.5 Z 0 VH = VCC OR VL 5 4 2 0 -2 -4 -5 TIME (10ns/DIV) Y-Z
DRIVER OUTPUT (V)
FIGURE 29. DRIVER WAVEFORMS, LOW TO HIGH (ISL32172E, ISL32174E, ISL32179E)
16
DRIVER OUTPUT (V)
FIGURE 30. DRIVER WAVEFORMS, HIGH TO LOW (ISL32172E, ISL32174E, ISL32179E)
FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Typical Performance Curves
VCC = VL = 3V DI 0 DRIVER OUTPUT (V) DRIVER OUTPUT (V) DRIVER + CABLE DELAY 3.0 1.5 0 -1.5 -3.0 3.0 1.5 Y-Z 0 -1.5 -3.0 +125C TIME (80ns/DIV) +85C Y-Z (~288ns)
VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued)
32Mbps 3 DRIVER INPUT (V) VCC = VL = 4.5V DI 0 DRIVER OUTPUT (V) DRIVER OUTPUT (V) DRIVER + CABLE DELAY 4.5 3.0 1.5 0 -1.5 -3.0 -4.5 4.5 3.0 1.5 0 -1.5 -3.0 -4.5 (~472ns) 32Mbps 5 DRIVER INPUT (V)
Y-Z
+85C
Y-Z
+125C TIME (80ns/DIV)
FIGURE 31. WORST CASE (NEGATIVE) FIVE PULSE DRIVER WAVEFORMS DRIVING 200 FEET (62m) OF CAT5 CABLE (SINGLE TERMINATED WITH 121) (ISL32172E, ISL32174E, ISL32179E)
FIGURE 32. WORST CASE (NEGATIVE) FIVE PULSE DRIVER WAVEFORMS DRIVING 328 FEET (100m) OF CAT5 CABLE (SINGLE TERMINATED WITH 121) (ISL32172E, ISL32174E, ISL32179E)
Die Characteristics
SUBSTRATE AND QFN THERMAL PAD POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 1682 PROCESS: Si Gate BiCMOS
17
FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 16 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 16 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E
Package Outline Drawing
L24.4x4C
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/06
4X 2.5 4.00 A B 19 20X 0.50 24 PIN #1 CORNER (C 0 . 25)
PIN 1 INDEX AREA
18
1
4.00
2 . 50 0 . 15
13
(4X)
0.15 12 7 0.10 M C A B 0 . 07 24X 0 . 23 + 0 . 05 4 24X 0 . 4 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0 . 1
( 3 . 8 TYP )
C BASE PLANE
SIDE VIEW
SEATING PLANE 0.08 C
(
2 . 50 ) ( 20X 0 . 5 )
C ( 24X 0 . 25 ) ( 24X 0 . 6 )
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
19
FN6824.0 December 16, 2008
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B D N (N/2)+1 A
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
A A1 A2 b c D E E1 e
H
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00
Max 0.05 0.05 +0.05/-0.06 +0.05/-0.06 0.10 Basic 0.10 Basic 0.15 Reference Rev. F 2/07
E
E1
1 B TOP VIEW
(N/2)
0.20 C B A 2X N/2 LEAD TIPS
C SEATING PLANE
e
0.05
L L1 NOTES:
b 0.10 C N LEADS SIDE VIEW
0.10 M C A B
1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X"
c
END VIEW
L1
A
A2 GAUGE PLANE 0.25 A1 DETAIL X L 0 - 8
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN6824.0 December 16, 2008

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